ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 82

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

10. External Interrupts
10.1
82
Pin Change Interrupt Timing
Atmel ATmega16/32/64/M1/C1
The External Interrupts are triggered by the INT3:0 pins or any of the PCINT23..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT23..0 pins are
configured as outputs. This feature provides a way of generating a software interrupt. The pin
change interrupt PCI2 will trigger if any enabled PCINT23..16 pin toggles. The pin change
interrupt PCI1 will trigger if any enabled PCINT14..8 pin toggles. The pin change interrupt
PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK3, PCMSK2, PCMSK1 and
PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change
interrupts on PCINT26..0 are detected asynchronously. This implies that these interrupts can
be used for waking the part also from sleep modes other than Idle mode.
The INT3:0 interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrupt Control Register A – EICRA. When
the INT3:0 interrupts are enabled and are configured as level triggered, the interrupts will trig-
ger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on
INT3:0 requires the presence of an I/O clock, described in
tion” on page
this interrupt can be used for waking the part also from sleep modes other than Idle mode. The
I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no
interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as
described in
An example of timing of a pin change interrupt is schown in Figure 10-1.
Figure 10-1. Timing of a pin change interrupts
PCINT[i]
pin
clk
pcint_set/flag
PCINT[i] pin
pcint_in[i]
pcint_syn
pin_sync
pin_lat
D
LE
PCIF
“Clock Systems and their Distribution” on page
29. Low level interrupt on INT3:0 is detected asynchronously. This implies that
clk
Q
n
pin_lat
D
Q
pin_sync
(of PCMSK
PCINT[i] bit
n
)
pcint_in[i]
0
7
clk
“Clock Systems and their Distribu-
29.
D
Q
pcint_sync
D
Q
pcint_set/flag
7647G–AVR–09/11
D
Q
(interrupt
PCIF
flag)
n