L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 90

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Acl_Protocol_Ace_Map_Index_Table
Description: This table converts a protocol index into an ACE map index.
Table 80. Acl_Protocol_Ace_Map_Index_T
Table 81. Acl_Protocol_Ace_Map_Index_T
This table is addressed by the concatenation of the acl_index[5:0] value and a protocol index value
(acl_protocol_index[2:0]). Each entry in this table is a 7-bit index into
Acl_Protocol_Port_Ace_Map_Table.
This table allows the eight protocol indexes appearing in 64 ACLs to address as many as 256 ACE maps. The fol-
lowing figure shows where this table fits in the processing pipeline.
90
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
protocol_ace_map_index[6:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
1
Field Name
2
Parameter
3
4
5
Figure 61. Acl_Protocol_Ace_Map_Index_Table Register Diagram
6
7
8
(continued)
9
ACL Index
10
Offset = 0.24
Mode = R/W
Parameters
Figure 62. ACL Processing Pipeline
11
Agere Systems - Proprietary
12
able
able
13
0x0004_2800
ACE Map Index Table
14
ACL Result Tables
Register Parameters
Protocol Number
Value
Field Parameters
ACE Map Table
2048
Protocol Table
512
NA
15
ACL Result
1
4
4
Encoder
The ACE map index value.
16
17
ACE Map
ACE Index
18
19
20
21
Description
22
9
23
8
24
7
protocol_ace_map_index[6:0]
25
6
Preliminary Data Sheet
26
5
27
4
Agere Systems Inc.
28
3
29
2
30
1
April 2006
31
0