L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 233

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Supervisor_Int_Mask
Description: supervisor_access related interrupt mask.
Table 323. Supervisor_Int_Mask Register Parameters
Table 324. Supervisor_Int_Mask Field Parameters
This register shows the current state of the indication mask. Mask bits are set via Supervisor_Int_Mask_Set and
cleared via Supervisor_Int_Mask_Clear.
For the definitions of the various mask bits, see Supervisor_Ind, page 228.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
int_mask[15:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
Field Name
1
2
3
4
5
6
Figure 246. Supervisor_Int_Mask Register Diagram
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
7
(continued)
8
9
0x000c_c45c
Agere Systems - Proprietary
10
Instances = 1
Offset = 0.16
Parameters
Mode = RO
Value
11
NA
NA
4
1
4
1
12
13
14
15
16
Various interrupt mask bits.
17
18
19
20
21
22
Description
23
8
24
7
25
6
26
5
27
4
28
3
29
2
ET4148-50
30
1
31
0
233