L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 126

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Layer_2_Src_Port_Mask_Table
Description: Enables the limiting of destinations based on source port.
Table 151. Layer_2_Src_Port_Mask_Table Register Parameters
Table 152. Layer_2_Src_Port_Mask_Table Field Parameters
Source port masking is used to limit the destination ports reachable from each source port. There is a mask in the
table for each of the system’s source ports.
126
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
src_port_mask[57:0]
0
4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
1
REFERENCE
Field Name
Parameter
2
PORT
3
REFERENCE
4
SU7
57
Figure 114. Port Numbering Scheme (Mask Bits and Table Indexing)
5
PORT
SU6
Figure 113. Layer_2_Src_Port_Mask_Table Register Diagram
56
6
7
XG1
60
8
(continued)
Mode = R/W
Offset = 0.6
Instances = 1
Reset = 0
XG0
50
9
SU1
Parameters
51
SU1
10
49
PORT NUMBERING SCHEME (TABLE INDEXING)
SU0
11
50
SU0
48
Agere Systems - Proprietary
PORT NUMBERING SCHEME (MASK BITS)
0x000c_4200
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
12
XG1
49
G47
47
Value
13
400
src_port_mask[31:0]
NA
50
XG0
1
8
8
48
G46
14
46
G47
15
47
G45
The source port mask.
45
16
src_port_mask[57:32]
G46
46
G44
44
17
G45
45
18
19
G44
44
20
Description
21
G3
3
22
9
G2
2
23
8
G3
3
24
7
G1
1
Preliminary Data Sheet
25
6
G2
2
G0
0
26
5
G1
1
27
4
Agere Systems Inc.
G0
0
28
3
29
2
April 2006
30
1
31
0