L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 244
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L-ET4148-50C-DB
Manufacturer Part Number
L-ET4148-50C-DB
Description
Manufacturer
LSI
Datasheet
1.L-ET4148-50C-DB.pdf
(298 pages)
Specifications of L-ET4148-50C-DB
Lead Free Status / RoHS Status
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ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Supervisor_Statistics_Transfer_Status
Description: Indicates the status of a statistics block transfer.
Table 342. Supervisor_Statistics_Transfer_Status Register Parameters
Table 343. Supervisor_Statistics_Transfer_Status Field Parameters
This register provides basic status for statistics block transfers. A statistics block transfer is initiated by writing the
block’s transfer destination address to Supervisor_Statistics_Transfer_Addr. Upon initiation of the trans-
fer, statistics_transfer_busy is automatically asserted and remains asserted throughout the duration of the
transfer. At the completion of the transfer, statistics_transfer_busy is deasserted and
statistics_transfer_done is asserted. statistics_transfer_done is also made available to the super-
visor as an interrupt-generating indication. The supervisor must write a one to the bit position of
statistics_transfer_done in order to deassert the bit and cancel its indication.
244
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
statistics_transfer_done
statistics_transfer_busy
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Field Name
Parameter
2
3
4
Figure 257. Supervisor_Statistics_Transfer_Status Register Diagram
5
6
7
(continued)
8
9
10
11
Instances = 1
Instances = 1
Offset = 0.30
Offset = 0.31
Mode = R/W
Parameters
Mode = RO
Agere Systems - Proprietary
12
13
0x000c_c470
14
Value
15
NA
NA
4
1
4
1
16
17
This bit is asserted upon the completion of a statis-
tics block transfer. It is reset by writing a one to its
bit position.
This bit is asserted during the transfer of the statis-
tics block to indicate that such a transfer is in pro-
cess.
18
19
20
21
22
23
8
24
7
Description
25
6
Preliminary Data Sheet
26
5
27
4
28
3
Agere Systems Inc.
29
2
30
1
April 2006
31
0
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