L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 127

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Layer_2_Supervisor_Route_Port
Description: Identifies the supervisor’s route port.
Table 153. Layer_2_Supervisor_Route_Port Register Parameters
Table 154. Layer_2_Supervisor_Route_Port Field Parameters
When a receive packet’s MAC source address is found in the address table but the source VLAN and destination
VLAN do not match and supervisor routing is enabled, this port is added to the packet’s destination port map.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
supervisor_route_port[5:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
REFERENCE
1
Parameter
Field Name
2
PORT
3
SU7
4
57
5
SU6
Figure 115. Layer_2_Supervisor_Route_Port Register Diagram
56
6
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
SU1
9
51
Figure 116. Port Numbering Scheme
10
SU0
50
Agere Systems - Proprietary
Instances = 1
Offset = 0.26
Mode = R/W
11
Parameters
Reset = 0
PORT NUMBERING SCHEME
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
0x000c_4674
XG1
49
12
Value
13
XG0
NA
NA
48
4
1
4
1
14
G47
47
15
G46
46
16
The supervisor route port number.
17
G45
45
18
G44
44
19
20
21
22
Description
23
8
G3
3
24
7
G2
2
25
6
G1
26
1
5
27
4
G0
0
28
3
ET4148-50
29
2
30
1
31
0
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