L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 145

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Mdio_Mode
This register is used to define the characteristics of the MDIO clock. The period of the MDIO clock is established by
mdio_clk_period[7:0]. The value of this field establishes a terminal count which, in turn, defines the half-
clock period for the MDIO clock. A free-running counter counts up until reaching mdio_clk_period[7:0]. When
this value is reached, the free-running counter is reset to zero and the MDIO clock signal is toggled. Larger values
of mdio_clk_period[7:0] result in lower MDIO clock frequencies. For example, based on a 250 MHz core
clock frequency, an mdio_clk_period[7:0] value of 25 results in an MDIO clock frequency of 5 MHz.
mdio_clk_period[7:0] must be set to a minimum value of 1.
mdio_clk_offset[7:0] is used to establish a delay between the active edge of the MDIO clock and any transi-
tion on or sampling of MDIO data. When the free-running counter defined above is equal to
mdio_clk_offset[7:0], a data transition or sample occurs. mdio_clk_offset[7:0] must be set to a value
that is less than or equal to mdio_clk_period[7:0].
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Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
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Agere Systems - Proprietary
ET4148-50
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