L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 134

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet
Appendix A: Registers
Mac_Global_Mode
134
Table 166. Mac_Global_Mode Field Parameters (continued)
inject_offset_polarity
loopback_delay_select[1:0]
loopback_amplitude_select
inject_offset_2
inject_offset_1
inject_offset_0
sw_reset_control
rprog[5:0]
set_resistor_value_{0..2}[2:0]
force_resistor_{0..2}
resistor_compensation_status_{0..2}[2:0]
Field Name
(continued)
(continued)
Agere Systems - Proprietary
Offset = 12.12
Offset = 12.13
Spacing = 0.8
Spacing = 0.8
Spacing = 0.8
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 3
Instances = 3
Instances = 3
Offset = 8.18
Offset = 8.19
Offset = 8.21
Offset = 8.22
Offset = 8.23
Offset = 8.24
Offset = 8.25
Offset = 8.26
Offset = 12.9
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
Mode = RO
This bit establishes the polarity of the offset specified
by inject_offset{0..2}.
0 = positive polarity offset.
1 = negative polarity offset.
Selects a delay value when the SGMII is operating in
a serial loop back mode.
00
01
10
This bit selects one of two amplitudes for serial loop
back of the SGMII channels.
0 = 400 mV.
1 = 100 mV.
Asserting this bit causes an offset current of level 2
to be injected into the SGMII data.
Asserting this bit causes an offset current of level 1
to be injected into the SGMII data.
Asserting this bit causes an offset current of level 0
to be injected into the SGMII data.
Provides a software reset control to the device.
PLL parameter. Bits 4, 2, 1, and 0 of this value are
inverted between the register and the PLL. This is
done so that the reset value of 0 appears at the PLL
as 01_0111
This value is used in the SGMII termination block if
the corresponding force_resistor bit is asserted.
There are three independent termination control
groups serving the 48 SGMII ports.
When the SGMII termination compensation function
is disabled, a high on this bit enables the application
of the termination value specified in
set_resistor_value[2:0]. There are three independent
termination control groups serving the 48 SGMII
ports.
This field returns the resistor compensation results.
There are three independent termination control
groups serving the 48 SGMII ports.
2
2
2
= 400 ps.
= 100 ps.
= –100 ps.
2
.
Description
Preliminary Data Sheet
Agere Systems Inc.
April 2006