L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 269

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix B: Configuration
Ethernet Interfaces
PHYs
MDIO. The external PHY devices are configured and controlled via three MDIO interfaces. These interfaces are
accessed via the Mdio_Control, Mdio_Mode, and Mdio_Status registers.
The Mdio_Control register is used to issue read and write commands to the ET4148-50’s MDIO controller. To
issue a write command, the supervisor first sets up the parameters of the command (e.g., MDIO register address,
port select, device select, etc.) by writing to Mdio_Control with an mdio_opcode[1:0] value of 00
parameters have been established, the write data is then written to Mdio_Control and the command is automat-
ically executed.
A read command starts off similarly: the supervisor sets up all of the various parameters with an opcode of 11
This opcode results in an immediate initiation of the read command. The mdio_busy bit remains asserted
throughout the execution of the command. Once mdio_busy is deasserted by the ET4148-50, the read data is
available in the mdio_addr_data[15:0] field.
A separate register, Mdio_Status, is available for polling the state of the MDIO controller. The mdio_busy bit in
this register has the same meaning as the version of the bit that appears in the Mdio_Control register. The
mdio_done bit is asserted at the completion of a command. This bit remains asserted until a one is written to its
position within Mdio_Status by the supervisor.
MDIO (continued). The Mdio_Mode register is used to define the characteristics of the MDIO clock. The period of
the clock is defined by the mdio_clk_period[7:0] field. Larger values of mdio_clk_period[7:0] result in
lower MDIO clock frequencies. The mdio_clk_offset[7:0] is used to establish a delay between the MDIO
clock and the transition or sampling of MDIO data.
SerDes. The four 1.25 GHz SerDes that make up the four 1 Gbit/s SFP interfaces require a certain amount of
attention from the supervisor. Access to the control and status registers within the SFP SerDes is available via the
Serdes_Control_{4} register.
The eight 3.125 GHz SerDes that make up the two 10 Gbits/s XAUI interfaces require a certain amount of attention
from the supervisor. Access to the control and status registers within the XAUI SerDes is available via the
Serdes_Control_{5} register.
Both 8-bit and 16-bit access commands are available. These two command types share a common 32-bit register
location. In other words, the format of the fields at this register offset depends on the type of command being exe-
cuted. The target SerDes register address for the command and the write data (for write commands) are written to
serdes_addr[15:0] (or serdes_addr[7:0]) and serdes_wr_data[15:0] (or serdes_wr_data[7:0]),
respectively. Next, the access command code is written to the access_command[2:0] field at the same time that
the command_start bit is asserted.
Setting the command_start bit initiates the specified command. The serdes_command_busy bit is asserted to
indicate that the command is being executed. At the completion of the command, serdes_command_done is
asserted to indicate that read data is valid (in the case of a read command) and that a subsequent command may
be issued. The serdes_command_done bit remains asserted until the initiation of a subsequent command.
Link Aggregation
Link aggregation enables multiple, parallel Ethernet links to appear to the ET4148-50 as if they were a single, logi-
cal link; thus providing an increase in bandwidth. No more than eight ports may be a part of any one aggregate.
(continued)
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
Agere Systems - Proprietary
2
ET4148-50
. Once the
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