L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 139

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Appendix A: Registers
Mac_Mode_{5..6}
Table 170. Mac_Mode_{5..6} Field Parameters (continued)
Agere Systems Inc.
less_aggress_mode
xgmac_rx_en
xgmac_flow_control_initiate_en
xgmac_rx_pause_en
Field Name
REFERENCE
(continued)
PORT
(continued)
XG1
60
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
XG0
50
Figure 129. Port Numbering Scheme
SU1
49
Agere Systems - Proprietary
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Offset = 0.28
Offset = 0.29
Offset = 0.30
Offset = 0.31
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
SU0
Parameters
48
PORT NUMBERING SCHEME
G47
47
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
G46
46
G45
45
When asserted, the minimum interframe gap for the
corresponding 10G port will always have a value
from 12 bytes to 15 bytes. When deasserted, the
interframe gap will be the average of 12 bytes ±
3 bytes.
Enables the reception of Ethernet packets. When
false, only MAC control packets are received.
This bit enables the initiation of flow control actions
on the part of the Ethernet MAC in response to flow
control indications from packet_buffer. If this
bit is deasserted, then the corresponding Ethernet
MAC never takes any flow control actions.
This bit must be asserted for the corresponding
Ethernet MAC to react to the reception of MAC flow
control packets.
G44
44
G3
3
Description
G2
2
G1
1
G0
0
ET4148-50
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