L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 231

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Supervisor_Ind_Mask_Set
Description: Sets bits in Supervisor_Ind_Mask.
Table 319. Supervisor_Ind_Mask_Set Register Parameters
Table 320. Supervisor_Ind_Mask_Set Field Parameters
Writing ones to bit locations in this register causes the corresponding bits in Supervisor_Ind_Mask to be set.
For the definitions of the various mask set bits, see Supervisor_Ind, page 228.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
ind_mask_set[15:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
1
Field Name
2
3
4
5
6
Figure 244. Supervisor_Ind_Mask_Set Register Diagram
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
9
10
0x000c_c454
Agere Systems - Proprietary
Instances = 1
11
Offset = 0.16
Parameters
Mode = WO
Value
12
NA
NA
4
1
4
1
13
14
15
16
17
Various indication mask set bits.
18
19
20
21
22
23
8
Description
24
7
25
6
26
5
27
4
28
3
29
2
ET4148-50
30
1
31
0
231