L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 249

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L-ET4148-50C-DB

Manufacturer Part Number
L-ET4148-50C-DB
Description
Manufacturer
LSI
Datasheet

Specifications of L-ET4148-50C-DB

Lead Free Status / RoHS Status
Supplier Unconfirmed
Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Tx_Collision_Histogram
Description: Statistics counters.
Table 350. Tx_Collision_Histogram Register Parameters
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
800
12
0
4
8
Parameter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
2
3
4
5
6
Figure 262. Tx_Collision_Histogram Register Diagram
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
9
10
0x0004_5000
Agere Systems - Proprietary
11
Value
1000
1000
NA
NA
12
1
1
13
14
15
16
17
18
19
tx_excessive_collision_packets[15:0]
tx_multiple_collision_packets[15:0]
tx_single_collision_packets[15:0]
20
tx_late_collision_packets[15:0]
tx_deferred_packets[15:0]
21
22
23
8
24
7
25
6
26
5
27
4
28
3
29
2
ET4148-50
30
1
31
0
249

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