L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 136

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet
Appendix A: Registers
Mac_Mode_{0..4}
136
Table 168. Mac_Mode_{0..4} Field Parameters (continued)
input_select_{}{0..9}[1:0]
speed_mode_force_{}{0..9}[1:0]
good_link_force_{}{0..9}
full_duplex_force_{}{0..9}
auto_negotiate_en_{}{0..9}
restart_auto_negotiation_{}{0..9}
gmac_tx_flush_{}{0..9}
gmac_port_speed_{}{0..9}[1:0]
gmac_port_loopback_en_{}{0..9}
Field Name
(continued)
(continued)
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Offset = 0.17
Offset = 0.19
Offset = 0.21
Offset = 0.22
Offset = 0.23
Offset = 0.24
Offset = 0.25
Offset = 0.26
Offset = 0.28
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
Mode = RO
Agere Systems - Proprietary
This field is used to select the source of receive data and
receive clocks for those Ethernet ports that support both
SGMII and SerDes interfaces. This field is encoded as
follows:
00
01
10
11
Causes the speed mode of the associated
1 Gbit/s link to be forced to the specified setting. This field
is only valid when good_link_force is asserted.
speed_mode_force[1:0] is defined as follows:
00
01
10
11
When asserted, associated link is forced to operate as if
it has detected a valid link signal. The assertion of this bit
also enables speed_mode_force[1:0] and
full_duplex_force.
When asserted, the associated PHY is forced into a full-
duplex mode of operation. This signal is only valid when
good_link_force is asserted.
When asserted, autonegotiation is enabled for the asso-
ciate PHY.
Autonegotiation may be forced to be restarted by assert-
ing and then immediately deasserting this bit. The rising
edge (0-to-1 transition) is detected in order to force a sin-
gle autonegotiation.
When asserted, the associated PHY accepts transmit
data from packet_buffer at the maximum data rate
and then discards it without transmitting it. Changes to
this mode bit only take effect between transmit packets.
Indicates the port speed of the associated PHY.
00
01
10
11
When asserted, all transmit packets are looped back to
the receive path by the associated SGMII interface. Net-
work reception is disabled during loopback. Changes to
this mode bit take effect immediately. This may cause the
transmission or reception of one or more defective pack-
ets.
2
2
2
2
2
2
2
2
2
2
2
2
= data disabled, SGMII clock.
= reserved.
= reserved.
= data disabled, SGMII clock.
= SGMII data and clock.
= SerDes data and clock.
= 10 Mbits/s.
= 100 Mbits/s.
= 1 Gbit/s.
= 10 Mbits/s.
= 100 Mbits/s.
= 1 Gbit/s.
Description
Preliminary Data Sheet
Agere Systems Inc.
April 2006