L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 132

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Layer_2_Vlan_Port_State_Table
Description: Maintains the spanning tree state on a per-port and per-VLAN basis.
Table 163. Layer_2_Vlan_Port_State_Table Register Parameters
Table 164. Layer_2_Vlan_Port_State_Table Field Parameters
In order to support per VLAN spanning tree, the spanning tree state of each port must be maintained on a per-
VLAN basis. This table provides this information to the bridging function.
This table is addressed by a concatenation of the packet’s receive port and the packet’s VLAN index:
address[13:0] = { rx_port[5:0], vlan_index[7:0] }
132
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
stp_state[1:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
Field Name
2
3
REFERENCE
4
5
Figure 123. Layer_2_Vlan_Port_State_Table Register Diagram
PORT
6
7
XG1
60
(continued)
8
XG0
50
9
Figure 124. Port Numbering Scheme
10
SU1
49
PORT NUMBERING SCHEME
Instances = 1
Offset = 0.30
11
Mode = R/W
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
Parameters
Agere Systems - Proprietary
SU0
0x000a_0000
48
12
62464
15616
Value
G47
13
47
NA
1
4
4
14
G46
46
15
G45
45
16
G44
The port/VLAN STP state.
00
01
10
11
17
44
2
2
2
2
18
= disabled
= blocking
= learning
= forwarding
19
20
21
G3
3
22
G2
Description
23
2
8
24
7
Preliminary Data Sheet
G1
1
25
6
G0
0
26
5
Agere Systems Inc.
27
4
28
3
April 2006
29
2
30
1
31
0