L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 110

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Layer_2_Key_Table_0
Description: The first stage of a MAC address look-up is performed by this table.
Table 121. Layer_2_Key_Table_0 Register Parameters
Table 122. Layer_2_Key_Table_0 Field Parameters
This first stage of a MAC address look-up involves the use of a single record containing three keys. The three keys
are compared against the search argument. The results of these comparisons serve to select one of the four index
values for use in the next stage of the look-up.
110
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
layer_2_key_{0..2}[47:0]
12
16
20
0
4
8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
1
Field Name
2
3
4
5
6
7
Figure 91. Layer_2_Key_Table_0 Register Diagram
8
(continued)
9
0x000c_4600
Spacing = 8.0
Instances = 3
Offset = 0.16
Mode = R/W
Parameters
10
Value
11
NA
NA
24
24
1
1
Agere Systems - Proprietary
12
13
layer_2_key_0[31:0]
layer_2_key_1[31:0]
layer_2_key_2[31:0]
14
15
A set of 48-bit MAC address values. These
values are compared against the search argu-
ment. The results of these comparisons are
used to select one of four index values for use
in the next stage of the look-up.
16
17
18
19
20
Description
21
layer_2_key_0[47:32]
layer_2_key_1[47:32]
layer_2_key_2[47:32]
22
23
8
24
7
25
6
Preliminary Data Sheet
26
5
27
4
Agere Systems Inc.
28
3
29
2
30
April 2006
1
31
0