L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 172

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Packet_Buffer_Port_Speed
Description: Provides the port speed information to the traffic shapers.
Table 227. Packet_Buffer_Port_Speed Register Parameters
Table 228. Packet_Buffer_Port_Speed Field Parameters
This register provides per-port interface speed information to the traffic shapers. This register does not actually
affect the speed of the Ethernet ports; it merely informs the packet buffer of the speed at which each port is operat-
ing.
172
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
port_speed_{0..47}[1:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
REFERENCE
1
Field Name
Parameter
2
PORT
3
4
SU7
57
5
6
SU6
56
Figure 164. Packet_Buffer_Port_Speed Register Diagram
7
8
(continued)
9
Figure 165. Port Numbering Scheme
SU1
10
51
Instances = 48
11
Spacing = 4.0
Offset = 0.30
SU0
Mode = R/W
Parameters
Agere Systems - Proprietary
50
0x000c_bd00
12
PORT NUMBERING SCHEME
XG1
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
49
Value
13
192
192
NA
NA
1
1
14
XG0
48
15
G47
47
16
G46
17
46
The speed of the corresponding Ethernet MAC.
00
01
10
11
18
2
2
2
2
G45
45
= reserved
= 10 Mbits/s
= 100 Mbits/s
= 1 Gbit/s
19
G44
44
20
21
22
23
8
Description
24
7
G3
3
Preliminary Data Sheet
25
6
G2
2
26
5
27
4
G1
1
Agere Systems Inc.
28
3
G0
0
29
2
April 2006
30
1
31
0