L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 223

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Serdes_Control_{4}
Table 308. Serdes_Control_{4} Field Parameters
access_command[2:0]
command_start
serdes_wr_data[7:0]
or
serdes_wr_data[15:0]
serdes_wr_addr[7:0]
or
serdes_wr_addr[15:0]
serdes_command_busy
serdes_command_done
serdes_rd_data[15:0]
REFERENCE
PORT
XG1
60
Field Name
XG0
50
SU1
49
(continued)
SU0
48
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
G47
47
G46
46
Figure 237. Port Numbering Scheme
Agere Systems - Proprietary
G45
45
G44
44
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Offset = 0.28
Offset = 0.31
Offset = 4.16
Offset = 4.24
Offset = 4.16
Offset = 8.16
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
Mode = WO
Mode = WO
Offset = 4.0
Mode = RO
Offset = 8.0
Mode = RO
Offset = 8.1
Mode = RO
PORT NUMBERING SCHEME
or
or
G3
3
Defines the type of SerDes register access func-
tion to be performed:
Writing a one to this bit causes the execution of
the specified access command.
The 8-bit or 16-bit data word to be written to the
specified SerDes register. The width and offset of
this field must be consistent with the command
issued via access_command[2:0].
The 8-bit or 16-bit address to be used to specify
the desired SerDes register. The width and offset
of this field must be consistent with the command
issued via access_command[2:0].
This bit is asserted to indicate that the requested
SerDes registers access command is currently
being executed. While this bit is asserted, writes
to all fields of this register are ignored.
This bit is asserted to indicate that the requested
SerDes register access command has completed
operation. If the requested command was a read
command, then this bit serves as an indication
that serdes_rd_data[15:0] is valid.
Data from read commands is returned via this
field. For 8-bit reads, the data occupies the least
significant 8 bits of this field
(serdes_rd_data[7:0]).
000
100
010
110
xx1
G2
2
2
2
2
2
2
G1
= reserved
= 16-bit write (SerDes PRBS registers)
= 8-bit read (SerDes macro registers)
= 8-bit write (SerDes macro registers)
= 16-bit read (SerDes PRBS registers)
1
G0
0
Description
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
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