L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 11

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Pin Descriptions
Table 5. Miscellaneous Pins
TDI
TCK
TMS
TRST_N
TDO
MDIO_C22_(1:0)
MDC_C22_(1:0)
MDIO_C45
MDC_C45
SE
TM(2:0)
TST(9:0)
VM(1:0)
RREF(2:0)
VREF
RST_N
REFCLK_CORE
Pin Name
CMOS output C31
CMOS output 1{AH22}, 0{AG22}
CMOS output AK24
CMOS output 9{AK25}, 8{AF22}, 7{AJ24},
CMOS output 1{Y28}, 0{Y30}
CMOS input
CMOS input
CMOS input
CMOS input
CMOS input
CMOS input
CMOS input
CMOS input
(open drain)
(open drain)
(continued)
CMOS I/O
CMOS I/O
Type
REF
REF
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
E31
E30
D31
E29
1{AL24}, 0{AK22}
AL25
AJ26
2{D29}, 1{C30}, 0{B31}
6{AH24}, 5{AJ25}, 4{AL26},
3{AG23}, 2{AH23}, 1{AF24},
0{AJ23}
2{AF14}, 1{T4}, 0{B16}
C2
AA31
AJ22
Agere Systems - Proprietary
Pins #s
JTAG serial data in.
JTAG clock.
JTAG test mode select.
JTAG test reset. Active-low. Pull low
for normal operation.
JTAG serial data out.
Serial management data I/O signal.
Clause 22 compatible.
Serial management clock signal.
Clause 22 compatible.
Serial management data I/O signal.
Clause 45 compatible.
Serial management clock signal.
Clause 45 compatible.
Reserved—scan enable. Pull low for
normal operation.
Reserved—test mode select. Pull low
for normal operation.
Reserved—test mode output. Leave
unconnected.
Reserved—voltage monitor output.
Leave unconnected.
Bias reference—pull to ground with
individual 2.49 kΩ resistors.
Reference voltage—set to 1.23 V. ±
1%.
Chip reset, active-low. During pow-
erup, this signal should be held low
for at least 200 ns after power has
ramped and REFCLK_CORE
(25 MHz) is stable. If the system is
already powered up and stable, the
signal may be pulsed low for 200 ns
or more. See Device Reset in
Appendix B.
Reference clock for the core of the
chip. 25 MHz.
Description
ET4148-50
11