L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 3

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Contents
Preliminary Data Sheet
April 2006
Features .................................................................................................................................................................... 1
Benefits ..................................................................................................................................................................... 1
Target Applications ................................................................................................................................................... 1
Block Diagram........................................................................................................................................................... 1
Description ................................................................................................................................................................ 2
System Diagram........................................................................................................................................................ 2
Pin Descriptions ........................................................................................................................................................ 8
Memory Map ........................................................................................................................................................... 14
Functional Description............................................................................................................................................. 20
Data Structures ....................................................................................................................................................... 48
Electrical Specifications .......................................................................................................................................... 55
Physical Dimensions ............................................................................................................................................... 71
Appendix A: Registers............................................................................................................................................. 71
Agere Systems Inc.
Packet Reception.............................................................................................................................................. 20
VLAN Assignment............................................................................................................................................. 22
Access Control.................................................................................................................................................. 24
Bridging............................................................................................................................................................. 26
Flow Identification ............................................................................................................................................ 30
Policing ............................................................................................................................................................. 31
Storage ............................................................................................................................................................. 33
Retrieval............................................................................................................................................................ 34
VLAN Encapsulation......................................................................................................................................... 36
Packet Transmission ........................................................................................................................................ 38
Supervisor Packet Reception ........................................................................................................................... 39
Supervisor Packet Transmission ...................................................................................................................... 44
Supervisor_Rx_Fifo_{0..7}................................................................................................................................ 48
Supervisor_Rx_Packet ..................................................................................................................................... 49
Supervisor_Tx_Descriptor ................................................................................................................................ 51
Supervisor_Tx_Fifo_{0..1} ................................................................................................................................ 52
Supervisor_Tx_Packet...................................................................................................................................... 53
Supervisor_Tx_Packet_Segment ..................................................................................................................... 54
Absolute Maximum Ratings .............................................................................................................................. 55
ESD Protection ................................................................................................................................................. 55
Recommended Operating Conditions............................................................................................................... 56
Power Supply Consumption ............................................................................................................................. 56
Thermal Characteristics.................................................................................................................................... 56
PCI I/O Specification......................................................................................................................................... 57
JTAG I/O Specification ..................................................................................................................................... 57
SGMII I/O Transmit Specifications ................................................................................................................... 58
SGMII I/O Receive Specifications .................................................................................................................... 58
SFP—1.25 Gbits/s SerDes Specifications ....................................................................................................... 59
10G—3.125 Gbits/s SerDes Specifications ..................................................................................................... 62
Timing Diagrams............................................................................................................................................... 65
Registers, Records, and Fields......................................................................................................................... 71
Instance Numbering.......................................................................................................................................... 71
Line Caching..................................................................................................................................................... 71
Acl_Deny_Packets............................................................................................................................................ 72
Acl_En .............................................................................................................................................................. 73
Acl_Ip_Addr_Ace_Map_Index_Table ............................................................................................................... 74
Acl_Ip_Addr_Ace_Map_Table .......................................................................................................................... 75
Acl_Ip_Key_Table_0......................................................................................................................................... 76
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Agere Systems - Proprietary
Table of Contents
ET4148-50
Page
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