L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 144

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Mdio_Mode
Description: Defines the basic mode for the MDIO interfaces.
Table 176. Mdio_Mode Register Parameters
Table 177. Mdio_Mode Field Parameters
144
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
enbwp
iprog[3:0]
mdio_clk_offset[2:0]
mdio_clk_period[7:5]
kprog[2:0]
accept_jumbo_frames
short_ifg_mode
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
Field Name
2
3
4
5
6
7
(continued)
8
0x000c_8308
Figure 133. Mdio_Mode Register Diagram
9
Value
10
NA
NA
4
1
4
1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Offset = 0.16
Offset = 0.17
Offset = 0.21
Offset = 0.24
Offset = 0.27
Offset = 0.30
Offset = 0.31
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
11
Agere Systems - Proprietary
12
13
14
15
16
PLL parameter.
PLL parameter. iprog[2] is inverted between this
register and the PLL so that the default reset value
is 0100
This field establishes the delay between the active
edge of the MDIO clock and data.
This field defines the half-clock period of the MDIO
clock. mdio_clk_period[4:0] is hardwired to be
equal to 31.
PLL parameter. kprog[0] is inverted between this
register and the PLL.This has the effect of making
the after-reset value equal to 0100
When this bit is set, all ports may receive frames
greater than 1522 bytes.
When this bit is set, 10 Mbits/s and 100 Mbits/s
ports will transmit frames with an interframe gap of
11 bytes instead of 12 bytes. This bit should be
cleared for normal operation.
17
iprog[3:0]
18
19
2
.
20
21
22
Description
23
8
24
7
Preliminary Data Sheet
25
6
26
5
Agere Systems Inc.
kprog[2:0]
27
4
2
.
28
3
April 2006
29
2
30
1
31
0