L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 295

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix B: Configuration
Other Device Functions
PCI Initialization
For the PCI configuration space, the first 16 bytes are defined the same for all device types. In the ET4148-50, the
Header Type (offset 0x0E) is hardcoded to 0x00 and indicates that the configuration space header is type 0. This
type 0 header is represented in Figure 299.
The PCI specification requires implementation of five read-only fields. These include device ID, vendor ID, revision
ID, header type, and class code. Class code consists of three fields: base class code, subclass code, and pro-
gramming interface code. As mentioned above, the value of the header type field is 0x00. The values of these
remaining fields are as follows:
■
■
■
■
For initialization of the configuration space, program the command field (offset 0x04) to 0x0006. In addition, pro-
gram the base address register (offset 0x10) to support a 1 Mbyte memory space using a value of 0xXXX00000,
where X represents any arbitrary hexadecimal value. The least-significant nibble of the base address field has a
read-only value of 0xC, which specifies that the base address is prefetchable and maps into memory space.
Initially, per the specification, the PCI bus is little-endian; however, the ET4148-50 allows the reprogramming of the
bus to big-endian after PCI initialization. See the Supervisor Endian section below for information on reprogram-
ming the endianness. For more information on the PCI bus, see the PCI Local Bus Specification Rev. 3.0,
February 3, 2004.
Device ID (offset 0x02) = 0x1107
Vendor ID (offset 0x00) = 0x0700
Revision ID (offset 0x08) = 0x01
Class code
— Base class code (offset 0x09) = 0x06
— Subclass code (offset 0x0A) = 0x00
— Programming interface code (offset 0x0B) = 0x00
31
Max_Lat
BIST
Subsystem ID
Device ID
Status
(continued)
16
Figure 299. Type 0 Configuration Space Header
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Header Type
Class Code
Reserved
Min_Gnt
Expansion ROM Base Address
(continued)
Agere Systems - Proprietary
Base Address Registers
Cardbus CIS Pointer
Reserved
15
Latency Timer
Interrupt Pin
Subsystem Vendor ID
Command
Vendor ID
Cacheline Size
Interrupt Line
Revision ID
Capabilities
0
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
0x00
ET4148-50
295