L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 116

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

12
16
20
ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Layer_2_Key_Table_6
Description: The seventh and final stage of a MAC address look-up is performed by this table.
Table 133. Layer_2_Key_Table_6 Register Parameters
Table 134. Layer_2_Key_Table_6 Field Parameters
116
0
4
8
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
key_valid_{0..1}
layer_2_key_{0..1}[47:0]
layer_2_src_permit_{0..1}
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
2
Parameter
3
Field Name
4
5
6
7
Figure 97. Layer_2_Key_Table_6 Register Diagram
8
(continued)
layer_2_src_port_0[5:0]
layer_2_src_port_1[5:0]
9
10
0x0008_0000
11
131072
Value
4096
NA
Agere Systems - Proprietary
24
32
Spacing = 8.0
Spacing = 8.0
Spacing = 4.0
12
Instances = 2
Instances = 2
Instances = 2
Offset = 0.16
Offset = 16.8
Mode = R/W
Mode = R/W
Mode = R/W
1
Parameters
Offset = 0.0
13
layer_2_key_0[31:0]
layer_2_key_1[31:0]
14
15
16
17
This bit is asserted to indicate that the correspond-
ing key table entry is valid. If an invalid key is found
at the end of a look-up, then a look-up miss indica-
tion is returned in the same manner as if a valid
entry had not matched the search argument.
A set of 48-bit MAC address values. These values
are compared against the search argument. The
results of these comparisons are used to select one
of two associated data values.
This bit must be asserted for a packet whose
source address matches a valid associated key to
be forwarded.
18
19
layer_2_dest_map_index_0[8:0]
layer_2_dest_map_index_1[8:0]
20
21
layer_2_key_0[47:32]
layer_2_key_1[47:32]
22
23
8
Description
24
7
Preliminary Data Sheet
25
6
26
5
27
4
Agere Systems Inc.
28
3
29
2
April 2006
30
1
31
0