L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 69

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Electrical Specifications
Timing Diagrams
JTAG Timing
Table 45. JTAG Timing
TCK Period
TCK High
TCK Low
TDI, TMS to TCK Setup
TDI, TMS to TCK Hold
TCK to TDO Delay
Parameter
(continued)
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
TMS
TCK
TDO
TDI
TDO
Min
40
20
20
15
15
0
Agere Systems - Proprietary
Figure 36. JTAG Timing
t
DELAY
t
LOW
t
CYCLE
t
Typ
SETUP
—
—
—
—
—
—
t
HIGH
t
HOLD
Max
30
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ET4148-50
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