L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 27

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Functional Description
Bridging
The bridging process starts with both the Layer 2 destination and source addresses being submitted for a look-up.
The principal information returned is the destination map and the source port associated with the packet’s source
address. Other information returned includes the match/fail result status for each look-up, flow identifying tags,
(used in the flow identification process described below) and a Layer 2 access control flag.
The destination map provides a per-port indication of which ports are destinations for the packet. An asserted bit in
the map implies that the corresponding port is an intended destination. The look-up of the destination address
returns an initial destination map. This map is then modified through the application of various maps (adding desti-
nations) and masks (deleting destinations). The final resulting destination map is used in concert with the packet’s
priority information to identify the queues into which references to the receive packet are deposited.
First, the spanning tree state of the receive port/VLAN combination is used to modify the packet’s destination. The
blocking mask disables all destinations that should be unreachable to a receive port that is in the blocking state.
Note: The ET4148-50 treats the blocking and listening states as being functionally equivalent.
The learning mask deletes those destinations that should be unreachable to a receive port that is in the learning
state. If the receive packet’s source address is unknown or its receive port does not match the receive port associ-
ated with the source address in the address table, the ET4148-50’s learning queue is added to the packet’s list of
destinations.
Note: The link aggregation function makes it possible for a source address to appear on multiple receive ports
If the source address of the receive packet does exist in the address table, and the stored receive port number
matches the port number via which the packet was received, then the address table’s time stamp value for the
source address must be updated. This is a simple matter of writing the current time value to the time stamp table
location that corresponds to the current source address of the receive packet.
IGMP and user port snooping are performed next. For IGMP snooping, if the receive packet is an IGMP packet and
IGMP snooping is enabled, then the IGMP snooping queue is added to the destination map. Similarly, if the TCP or
UDP destination port number matches the user-defined snooping port number, then the user-port snooping queue
is added to the packet’s destination map.
If the VLAN associated with the receive packet does not match the VLANs associated with any of the destination
ports indicated in the destination map so far, then the packet is not going to be forwarded due to VLAN filtering.
However, if so enabled, the supervisor may receive these VLAN-filtered packet so that it may apply routing opera-
tions to these packets and allow them to communicate across VLAN boundaries. The supervisor’s routing queue is
used for this purpose.
The following three masks are applied unconditionally:
1. VLAN mask
2. Port aggregation mask
3. Source port mask
The VLAN mask is applied to delete all of the destinations in the destination map that are not members of the
receive packet’s VLAN.
within a very short time span. Ordinarily, these varying source ports would cause many unnecessary copies
of the packet to be forwarded to the learning queue. The use of a logical port number that groups together
the ports associated with an aggregate together under a single label eliminates these unnecessary learning
operations. Refer to Link Aggregation on page 269 for more information regarding the configuration of link
aggregates.
(continued)
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
Agere Systems - Proprietary
ET4148-50
27