L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 225

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Serdes_Control_{5}
Table 310. Serdes_Control_{5} Field Parameters
access_command[2:0]
command_start
serdes_wr_data[7:0]
or
serdes_wr_data[15:0]
serdes_wr_addr[7:0]
or
serdes_wr_addr[15:0]
serdes_command_busy
serdes_command_done
serdes_rd_data[15:0]
local_fault
remote_fault
lanes_not_deskewed
Field Name
(continued)
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
Offset = 12.24
Offset = 12.25
Offset = 12.26
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Offset = 0.28
Offset = 0.31
Offset = 4.16
Offset = 4.24
Offset = 4.16
Offset = 8.16
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
Mode = WO
Mode = WO
Offset = 4.0
Mode = RO
Offset = 8.0
Mode = RO
Offset = 8.1
Mode = RO
Mode = RO
Mode = RO
or
or
Agere Systems - Proprietary
Defines the type of SerDes register access function to be per-
formed:
Writing a one to this bit causes the execution of the specified
access command.
The 8- bit or 16-bit data word to be written to the specified Ser-
Des register. The width and offset of this field must be consis-
tent with the command issued via access_command[2:0].
The 8-bit or 16-bit address to be use to specify the desired Ser-
Des register. The width and offset of this field must be consis-
tent with the command issued via access_command[2:0].
This bit is asserted to indicate that the requested SerDes regis-
ters access command is currently being executed. While this bit
is asserted, writes to all fields of this register are ignored.
This bit is asserted to indicate that the requested SerDes regis-
ter access command has completed operation. If the requested
command was a read command, then this bit serves as an indi-
cation that serdes_rd_data[15:0] is valid.
Data from read commands is returned via this field. For 8-bit
reads, the data occupies the least significant 8 bits of this field
(serdes_rd_data[7:0]).
Indicates a fault at the local station such as failure to acquire
lane synchronization or lane deskew.
Indicates a fault at the far-end station.
This bit is asserted upon the detection of a not-deskewed event
for any of the lanes. Once such an event is detected, this bit is
asserted and remains asserted until cleared. This bit is cleared
by writing a 1 to its position.
000
100
010
110
xx1
2
2
2
2
2
= reserved
= 16-bit write (SerDes PRBS registers)
= 8-bit read (SerDes macro registers)
= 8-bit write (SerDes macro registers)
= 16-bit read (SerDes PRBS registers)
Description
ET4148-50
225