L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 39

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Functional Description
Supervisor Packet Reception
Data Structures
The receive structures established within the supervisor’s memory system consist of a series of circular FIFOs.
The starting and ending locations of the FIFOs are defined through a series of registers within the ET4148-50
(Supervisor_Rx_Fifo_Limits_{0..7}). These starting and ending locations of each FIFO remain static once
configured by the supervisor.
Read and write pointers (Supervisor_Rx_Fifo_Ptr_{0..7}) are used during the operation of the FIFOs. The
ET4148-50 advances the write pointers as packet data is stored in the FIFO space, and the supervisor advances
the read pointer as it processes and discards the packets.
All packets transferred into the supervisor’s receive queues are treated integrally. In other words, if the space
remaining in the FIFO before its physical endpoint (not to be confused with its logical endpoint) is not sufficient to
accommodate a maximum length packet, then the packet is stored at the beginning of the FIFO’s physical range.
The discontinuity caused by the gap left at the end of the physical range of the FIFO is handled by means of a
32-bit pointer that is written to the FIFO as the first word of the packet’s data structure. The 32-bit pointer
(Supervisor_Rx_Packet.packet_start_ptr[31:2]) points to where the packet can actually be found.
Normally, this pointer points to the very next 32-bit word (as in the case of contiguously spaced receive packets).
However, when a discontinuity is introduced as a consequence of keeping packets integral, the pointer points to
the start of the FIFO’s physical range rather than the next 32-bit word location.
INSUFFICIENT ROOM FOR A
MAXIMUM LENGTH PACKET, SO...
...THE PACKET IS STORED AT
THE START OF THE FIFO.
FIFO PHYSICAL START
FIFO PHYSICAL END
FIFO LOGICAL START
FIFO LOGICAL END
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
Figure 17. Receive Circular FIFO Structure
(continued)
Agere Systems - Proprietary
Supervisor_Rx_Fifo_Limits_{n}.rx_fifo_start_ptr[31:2]
Supervisor_Rx_Fifo_Ptr_{n}.wr_ptr[31:2]
Supervisor_Rx_Fifo_Limits_{n}.rx_fifo_first_ptr[31:2]
Supervisor_Rx_Fifo_Ptr_{n}.last_ptr[31:2]
Supervisor_Rx_Fifo_Limits_{n}.rx_fifo_end_ptr[31:2]
FIFO FILL DIRECTION
ET4148-50
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