L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 266

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Preliminary Data Sheet
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
April 2006
Appendix B: Configuration
This chapter describes the methods for configuring the various features of the ET4148-50.
General
The supervisor’s access to the various registers within the ET4148-50 is via a 32-bit PCI bus. Many of the fields
and records that must be configured by the supervisor are wider than 32 bits. In general, the updating of a partial
word or record may cause unpredictable behavior. To prevent this, the ET4148-50 includes line caches where nec-
essary to ensure that integral records are always written to these registers.
Packet Buffer
The packet buffer in the ET4148-50 is self-configuring. The configuration process is initiated by the supervisor by
simply asserting the free_buffer_initialization_start and
free_descriptor_initialization_start bits in the Packet_Buffer_Free_Buffer_Control and
Packet_Buffer_Free_Descriptor_Control registers, respectively. Upon completion of the initialization
sequence, the ET4148-50 asserts the free_buffer_initialization_done and
free_descriptor_initialization_done bits, accordingly.
Ethernet Interfaces
The ET4148-50 includes multiple instances of two types of Ethernet interfaces: 48 10/100/1000 Mbits/s Ethernet
ports and two 10 Gbits/s Ethernet ports. Various aspects of each of these interfaces must be properly configured in
order to achieve normal operation.
Media Access Controllers
The media access controllers (MACs) are primarily configured via the Mac_Mode registers. There are seven such
registers. The five registers corresponding to the 10/100/1000 Mbits/s Ethernet ports (Mac_Mode_{0..4}) each
have 10 records; one for each MAC associated with the a register. The two registers that correspond to the two
10 Gbits/s Ethernet ports (Mac_Mode_{5..6}) each have a single record for the single MAC associated with each
registers. Certain configuration criteria are associated with just one type of port or the other. Most, however, are
common among both types of MACs.
Port Enable. Each Ethernet MAC may be completely disabled by deasserting the corresponding port_en bit in
the Mac_Mode_{0..6} registers.
Receive Enable. The Ethernet MACs are disabled from receiving any network traffic unless their corresponding
gmac_rx_en_{0..9} or xgmac_rx_en bit is asserted.
Speed Mode (Multispeed Only). Generally, the speed of the 10/100/1000 Mbits/s Ethernet ports is established
automatically via autonegotiation with the system at the far end of the Ethernet link. The current speed setting is
available to the supervisor via gmac_port_speed_{0..9}[1:0]. The valid values of this field are defined in the
following table.
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