L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 294

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix B: Configuration
Other Device Functions
Device Reset
If possible, the ET4148-50 should be supplied with a reset signal (RST_N) that is separate from the powerup reset
for the rest of the system so that the ET4148-50 may be independently reset. If the device is powered up and the
core clock (REFCLK_CORE) is stable, a low going pulse of 200 ns or greater is sufficient to reset the device. Dur-
ing powerup, the reset signal should be held low for at least 200 ns after power has ramped and REFCLK_CORE
is stable. Figure 298 illustrates the desired reset operation. In this figure, RST_N is represented as both a continu-
ously low signal and a low-going pulse. The continuously low signal represents the reset during power up. The
pulse is representative of a reset when the device is powered up and REFCLK_CORE is stable.
Table 384. RST_N Timing
294
Parameter
Tclk_stable
Trst
POWER_RAMP
REFCLK_CORE
SY S_RST_N
RST_N
Period needed for core clock stabilization
Period needed after power ramps and core
clock is stable
Description
(continued)
Figure 298. RST_N Operation
Agere Systems - Proprietary
Tclk_stable
System Dependent
≥200 ns
Trst
Preliminary Data Sheet
Value
Agere Systems Inc.
April 2006