L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 146

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Mdio_Status
Description: Provides supervisor control of the MDIO interfaces.
Table 178. Mdio_Status Register Parameters
Table 179. Mdio_Status Field Parameters
This register provides basic status regarding MDIO access cycles.
mdio_busy provides the same information as the signal of the same name in Mdio_Control.
mdio_done is automatically asserted upon completion of an MDIO access cycle. This signal is also used as an
interrupt-generating indication to the supervisor. The supervisor must write a zero to this bit’s position to deassert
the bit and cancel the indication.
146
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
mdio_busy
mdio_done
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
Field Name
2
3
4
5
6
7
(continued)
8
Figure 134. Mdio_Status Register Diagram
9
10
0x000c_8304
Instances = 1
Instances = 1
11
Mode = R/W
Parameters
Mode = RO
Offset = 0.0
Offset = 0.1
Value
Agere Systems - Proprietary
NA
NA
4
1
4
1
12
13
14
15
16
17
This bit is asserted during the period that a previ-
ously initiated MDIO access cycle is running.
mdio_busy is asserted by a write of the access
cycle’s addressing parameters.
If a read cycle was posted, then the read data is
valid immediately after the deassertion of
mdio_busy. Reads of mdio_data[15:0] and
writes to any field of Mdio_Control are not allowed
while mdio_busy is asserted.
This bit is asserted at the completion of an MDIO
access cycle. The supervisor must write a zero to
this bit’s position in order to clear the indication.
18
19
20
21
22
23
8
Description
24
7
Preliminary Data Sheet
25
6
26
5
27
Agere Systems Inc.
4
28
3
29
2
April 2006
30
1
31
0