L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 73

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Acl_En
Description: Enables the individual ACLs.
Table 48. Acl_En Register Parameters
Table 49. Acl_En Field Parameters
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
acl_en[63:0]
0
4
Parameter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Field Name
2
3
REFERENCE
4
5
PORT
0x0004_2500
6
7
Value
XG1
60
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
NA
(continued)
NA
8
1
8
1
8
XG0
50
9
Figure 39. Acl_En Register Diagram
Figure 40. Port Numbering Scheme
10
SU1
49
Agere Systems - Proprietary
Instances = 1
Mode = R/W
11
Parameters
Offset = 0.0
SU0
48
12
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
PORT NUMBERING SCHEME
13
G47
47
14
acl_en[63:32]
acl_en[31:0]
G46
46
15
G45
16
45
17
Each bit of this field corresponds to an ACL. An
ACL is enabled when its bit is asserted. If an ACL is
disabled, it is considered to be empty, and a permit
action is implied.
G44
44
18
19
20
21
22
G3
3
23
8
Description
G2
2
24
7
25
6
G1
1
26
5
G0
0
27
4
28
3
29
2
ET4148-50
30
1
31
0
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