L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 140

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Mac_Status_{0..4}
Description: Indicates fundamental status for the Ethernet MACs.
Table 171. Mac_Status_{0..4} Register Parameters
Table 172. Mac_Status_{0..4} Field Parameters
140
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
prbs_error_{0..9}{}
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
0
Parameter
1
2
Field Name
3
REFERENCE
4
5
PORT
6
7
XG1
Figure 130. Mac_Status_{0..4} Register Diagram
60
(continued)
8
XG0
9
50
0x000c_8050
Figure 131. Port Numbering Scheme
10
SU1
49
Value
PORT NUMBERING SCHEME
128
NA
11
Agere Systems - Proprietary
Instances = 10
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
4
5
4
1
Spacing = 0.1
Offset = 0.22
Mode = R/W
Parameters
SU0
48
12
G47
13
47
14
G46
46
15
G45
45
16
This bit is asserted to indicate that an error has
occurred during PRBS testing of the corresponding
SGMII channel. This bit is cleared by writing a one
to its location. Writing a zero has no effect.
G44
17
44
18
19
20
21
G3
3
22
9
Description
G2
23
8
2
Preliminary Data Sheet
24
7
G1
1
25
6
G0
0
26
5
Agere Systems Inc.
27
4
28
3
April 2006
29
2
30
1
31
0