L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 105

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Layer_2_Dest_Map_Table
Description: The table of initial destination port maps.
Table 111. Layer_2_Dest_Map_Table Register Parameters
Table 112. Layer_2_Dest_Map_Table Field Parameters
This table is addressed by the layer_2_dest_map_index[8:0] value returned as part of the associated data
from the destination MAC address look-up. The value retrieved from this table is a destination port map. Bits are
asserted in these map values to indicate destinations for the packet. This initial port map is adjusted through sev-
eral steps of masking (eliminating destinations) and mapping (adding destinations).
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
dest_map[57:0]
0
4
REFERENCE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
PORT
Field Name
Parameter
2
SU7
3
57
4
SU6
56
5
6
Figure 81. Layer_2_Dest_Map_Table Register Diagram
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
SU1
51
9
Instances = 1
Mode = R/W
Parameters
Offset = 0.6
Figure 82. Port Numbering Scheme
10
SU0
50
0x000c_2000
Agere Systems - Proprietary
PORT NUMBERING SCHEME
11
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
Value
XG1
4096
49
12
512
NA
1
8
8
13
XG0
48
dest_map[31:0]
14
G47
15
47
The initial destination port map.
16
G46
46
dest_map[57:32]
17
G45
18
45
19
G44
44
20
Description
21
22
23
8
24
7
G3
3
25
6
26
5
G2
2
27
4
G1
1
28
3
ET4148-50
29
2
G0
0
30
1
31
0
105