L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 226

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet
Appendix A: Registers
Serdes_Control_{5}
226
Table 310. Serdes_Control_{5} Field Parameters (continued)
lanes_deskewed
lane_sync[3:0]
REFERENCE
PORT
Field Name
XG1
60
XG0
50
SU1
49
(continued)
SU0
48
(continued)
G47
Offset = 12.27
Offset = 12.28
47
Instances = 1
Instances = 1
Parameters
Mode = RO
Mode = RO
G46
46
Figure 239. Port Numbering Scheme
G45
45
Agere Systems - Proprietary
G44
44
This bit provides a real-time indication of whether or not all of
the associated SerDes lanes are deskewed.
Data from read commands is returned via this field. For 8-bit
reads, the data occupies the least significant 8 bits of this field
(serdes_rd_data[7:0]).
PORT NUMBERING SCHEME
G3
3
G2
2
G1
1
G0
0
Description
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
Preliminary Data Sheet
Agere Systems Inc.
April 2006