L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 52

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Data Structures
Supervisor_Tx_Packet
Description: A string of transmit packet data bytes.
Table 15. Supervisor_Tx_Packet Register Parameters
Table 16. Supervisor_Tx_Packet
This data structure is a single transmit packet. Every transmit packet is preceded by a priority[3:0] value and
a dest_map[57:0] vector. The packet data bytes start at byte offset 8 and continue from there. The byte located
at offset 8 must always be the first byte of packet’s 48-bit Layer 2 destination address field.
The supervisor must not included a CRC value with the packet. A CRC is automatically calculated and appended
during the transmission process.
52
Base Address
Structure Size
Structure Instances
Structure Spacing
priority[3:0]
dest_map[57:0]
<packet bytes>
0
4
8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
priority[3:0]
Parameter
1
2
Field Name
3
4
5
(continued)
6
7
8
Variable (multiple of 4)
Figure 26. Supervisor_Tx_Packet Data Structure
9
10
Variable
Variable
Variable
Value
11
12
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
Offset = 0.0
Offset = 0.6
Offset = 8.0
Agere Systems - Proprietary
13
<packet bytes>
dest_map[31:0]
14
15
16
dest_map[57:32]
17
18
The packet’s priority value.
The packet’s destination map. Asserted bits corre-
spond to selected transmit ports.
The transmit packet data bytes.
19
20
21
22
23
8
24
7
Description
25
6
26
5
Preliminary Data Sheet
27
4
28
3
29
2
Agere Systems Inc.
30
1
31
0
April 2006