L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 154

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Packet_Buffer_Acl_Log_Port
Description: Identifies the ACL logging port.
Table 194. Packet_Buffer_Acl_Log_Port Register Parameters
Table 195. Packet_Buffer_Acl_Log_Port Field Parameters
If the ACL look-up returns a log indication, then the port identified by this value is added to the packet’s destination
port map. Most typically, one of the supervisor’s queues (ports 50 through 57) are designated as the ACL logging
port.
154
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
acl_log_port[5:0]
REFERENCE
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
PORT
1
Parameter
Field Name
2
SU7
57
3
SU6
4
56
5
Figure 144. Packet_Buffer_Acl_Log_Port Register Diagram
6
7
SU1
51
(continued)
8
9
SU0
50
Figure 145. Port Numbering Scheme
10
XG1
49
11
Instances = 1
Offset = 0.26
Mode = R/W
Parameters
Agere Systems - Proprietary
0x000c_bc58
Reset = 0
XG0
12
48
Value
13
NA
NA
G47
4
1
4
1
47
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
PORT NUMBERING SCHEME
14
G46
46
15
G45
16
45
17
The ACL logging port number.
G44
44
18
19
20
21
22
G3
3
23
8
Description
G2
2
24
7
Preliminary Data Sheet
G1
25
6
1
26
5
G0
0
acl_log_port[5:0]
27
4
Agere Systems Inc.
28
3
29
2
April 2006
30
1
31
0