L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 164

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Packet_Buffer_Free_Descriptor_Control
Description: Free buffer list initialization controls.
Table 215. Packet_Buffer_Free_Descriptor_Control Register Parameters
Table 216. Packet_Buffer_Free_Descriptor_Control Field Parameters
Free descriptor list initialization controls.
164
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
free_descriptor_initialization_start
free_descriptor_initialization_done
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
2
Field Name
3
4
Figure 158. Packet_Buffer_Free_Descriptor_Control Register Diagram
5
6
7
8
(continued)
9
10
11
Instances = 1
Instances = 1
Offset = 0.30
Offset = 0.31
Parameters
Mode = WO
Mode = RO
Agere Systems - Proprietary
12
13
0x000c_bb74
14
Value
15
NA
NA
4
1
4
1
16
17
Writing a one to this bit starts the initialization process
for the free descriptor list.
This bit indicates that the initialization of the free
descriptor list is complete. This bit is deasserted dur-
ing the initialization process.
18
19
20
21
22
23
8
Description
24
7
25
6
Preliminary Data Sheet
26
5
27
4
28
3
Agere Systems Inc.
29
2
30
1
April 2006
31
0