L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 239

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Supervisor_Rx_Fifo_Limits
Description: Defines the dimensions of the supervisor’s receive packet FIFOs.
Table 334. Supervisor_Rx_Fifo_Limits Register Parameters
Table 335. Supervisor_Rx_Fifo_Limits Field Parameters
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
rx_fifo_start_ptr_{0..7}[31:2]
rx_fifo_end_ptr_{0..7}[31:2]
rx_fifo_first_ptr_{0..7}[31:2]
congestion_threshold_{0..7}[23:2]
12
0
4
8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
2
Field Name
3
4
5
6
Figure 252. Supervisor_Rx_Fifo_Limits Register Diagram
7
8
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
9
10
0x000c_c480
11
Agere Systems - Proprietary
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Offset = 12.8
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
12
Offset = 0.0
Offset = 4.0
Offset = 8.0
Value
rx_fifo_start_ptr[31:2]
rx_fifo_end_ptr[31:2]
rx_fifo_first_ptr[31:2]
128
NA
16
16
1
8
13
14
15
congestion_threshold[23:2]
16
17
Defines the location within supervisor memory of
the first 32-bit word of a receive FIFO.
Defines the location within supervisor memory of
the last 32-bit word of a receive FIFO.
Defines the location within supervisor memory of
the packet that the supervisor is currently using.
This value is maintained by the supervisor and
interpreted by the ET4148-50. It prevents the
ET4148-50 from overwriting packets that are either
currently in use or have not yet been examined by
the supervisor.
This field is reserved. Program to 0x3FFFFF.
18
19
20
21
22
23
8
Description
24
7
25
6
26
5
27
4
28
3
29
2
ET4148-50
30
1
0
0
0
0
31
0
0
0
0
0
239