L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 261

no-image

L-ET4148-50C-DB

Manufacturer Part Number
L-ET4148-50C-DB
Description
Manufacturer
LSI
Datasheet

Specifications of L-ET4148-50C-DB

Lead Free Status / RoHS Status
Supplier Unconfirmed
Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Vlan_Id_Table_{5..6}
Description: This table converts VLAN indexes into VLAN identifiers.
Table 368. Vlan_Id_Table_{5..6} Register Parameters
Table 369. Vlan_Id_Table_{5..6} Field Parameters
One of 256 VLAN indexes are assigned to each packet during ingress processing. This table is used to convert the
8-bit index back into a 12-bit VLAN identifier immediately prior to transmission.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
vlan_id[11:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
Field Name
2
3
4
REFERENCE
5
6
PORT
7
Figure 280. Vlan_Id_Table_{5..6} Register Diagram
8
XG1
60
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
9
XG0
50
10
Figure 281. Port Numbering Scheme
0x0007_5000
11
SU1
49
Agere Systems - Proprietary
Instances = 1
Offset = 0.20
Mode = R/W
PORT NUMBERING SCHEME
Parameters
12
32768
Value
1024
256
SU0
48
4
4
2
13
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
14
G47
47
15
G46
46
16
17
G45
45
18
The VLAN identifier as selected by the VLAN index.
G44
44
19
20
21
22
23
8
G3
3
24
7
vlan_id[11:0]
Description
25
6
G2
2
26
5
G1
1
27
4
G0
28
3
0
29
2
30
1
31
0
ET4148-50
261

Related parts for L-ET4148-50C-DB