L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 245

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Supervisor_Tx_Fifo_Limits
Description: Defines the dimensions of the supervisor’s transmit packet FIFOs.
Table 344. Supervisor_Tx_Fifo_Limits Register Parameters
Table 345. Supervisor_Tx_Fifo_Limits Field Parameters
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
tx_fifo_start_ptr_{0..1}[31:2]
tx_fifo_end_ptr_{0..1}[31:2]
tx_fifo_last_ptr_{0..1}[31:2]
tx_en_{0..1}
12
0
4
8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
Field Name
1
2
3
4
5
Figure 258. Supervisor_Tx_Fifo_Limits Register Diagram
6
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
9
10
0x000c_c500
Agere Systems - Proprietary
Offset = 12.31
Instances = 1
Instances = 1
Instances = 1
Instances = 1
Mode = R/W
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
Offset = 0.0
Offset = 4.0
Offset = 8.0
11
Value
NA
12
32
16
16
tx_fifo_start_ptr[31:2]
1
2
tx_fifo_end_ptr[31:2]
tx_fifo_last_ptr[31:2]
13
14
15
16
17
Defines the location within supervisor memory of
the first 32-bit word of a transmit FIFO.
Defines the location within supervisor memory of
the last 32-bit word of a transmit FIFO.
Defines the location within supervisor memory of
the last complete packet transmission FIFO entry.
This value is maintained by the supervisor and
interpreted by the ET4148-50. It prevents the
ET4148-50 from reading beyond the end of the
FIFO.
Enables transmission via the corresponding queue.
18
19
20
21
22
23
8
Description
24
7
25
6
26
5
27
4
28
3
29
2
ET4148-50
30
1
0
0
0
31
0
0
0
0
245