L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 293

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix B: Configuration
Other Networking Functions
Defining the FIFOs. The Supervisor_Rx_Fifo_Limits register is used to establish the physical extent of the
eight packet receive FIFOs in the supervisor memory space. The rx_fifo_start_ptr[31:2] and
rx_fifo_end_ptr[31:2] fields point to the first and last 32-bit words of each receive FIFO. The ET4148-50
deposits receive packets into contiguous locations between these two limits.
The rx_fifo_first_ptr[31:2] field is used by the supervisor to protect receive packets that have been
transferred across the PCI bus into the supervisor’s memory and which the supervisor has not yet finished using.
The supervisor sets rx_fifo_first_ptr[31:2] to point to the first word of the packet that it is currently work-
ing with. The ET4148-50 will not advance its write pointer beyond the point identified by
rx_fifo_first_ptr[31:2], thus preventing the overrunning of FIFO data.
Managing the FIFOs. As packets are transferred into a supervisor’s receive FIFO, two pointers are advanced by
the ET4148-50 to inform the supervisor of the state of the receive transfer process. These pointers reside in the
Supervisor_Rx_Fifo_Ptr register. There is one set of pointers for each of the eight queues.
The rx_fifo_wr_ptr[31:2] value indicates the location of supervisor memory currently being addressed dur-
ing write operations. This pointer is for informational purposes only and need not be monitored during normal oper-
ation.
The rx_fifo_last_ptr[31:2] value points to the start of the newest complete packet in the corresponding
receive FIFO. Once the supervisor has processed the packet identified by this pointer, the FIFO is considered
empty.
Statistics
The extent to which statistics require any configuration is that they must be reset to zero or some other starting
value prior to normal operation of the device. When any of the ET4148-50’s statistics counters reach their maxi-
mum value, they roll over to zero without notification and continue counting. Consequently, the statistics counters
must be sampled often enough such that the sample period is always less than the counters’ minimum roll over
period.
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
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Agere Systems - Proprietary
ET4148-50
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