L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 44

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Preliminary Data Sheet
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
April 2006
Functional Description
(continued)
Supervisor Packet Transmission
(continued)
Packet Transmission Queue
Two packet transmission queues are maintained within supervisor memory. Each queue consists of a series of
32-bit words that are pointers to packet descriptor blocks. One queue entry and, consequently, one packet descrip-
tor block, corresponds to a single packet. A single packet descriptor block may have more than one reference in
the packet transmission queues.
The physical limits of the packet transmission queues as well as their read and write pointers are defined by a
series of registers.
Packet Descriptor Blocks. Packet descriptor blocks are variable length lists of pointers and byte counts that iden-
tify the packet segments to be gathered up to form a transmit packet. By allowing packets to be segmented into
several pieces, the supervisor has the option of having catalogs of look-up result headers, Layer 2 headers, and
Layer 3 headers that can be concatenated to form a packet’s header. Packet bodies may also be cataloged and
warehoused in this fashion.
Each packet descriptor block consists of a one or more pairs of 32-bit words. The first 32-bit word is a pointer to a
packet segment. The second 32-bit word contains a byte count for the segment and a flag that indicates whether or
not the current segment is the last segment for the packet. The processing of these descriptor block records contin-
ues until a last flag is encountered.
Packet Segments. Packet segments are simple byte strings that make up the actual packet data. Packet seg-
ments may range in size from a single byte to 16 Kbytes.
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Agere Systems Inc.
Agere Systems - Proprietary