L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 171

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Packet_Buffer_Parity_Error_Info
Description: Provides the location of the occurrence of a parity error.
Table 225. Packet_Buffer_Parity_Error_Info Register Parameters
Table 226. Packet_Buffer_Parity_Error_Info Field Parameters
Upon the first occurrence of a parity error, this register stores and presents a value that identifies which device
experienced the error and the address within the device that was being accessed at the time of the error. Further
parity errors do not cause changes to the value held by this register. In order to reprime this register for the capture
of a subsequent error, all packet_buffer-related parity error indication bits in Packet_Buffer_Ind must first
be reset.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
memory_device[5:0]
memory_addr[14:0]
Parameter
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Field Name
0
1
2
3
Figure 163. Packet_Buffer_Parity_Error_Info Register Diagram
4
5
6
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
7
8
9
Agere Systems - Proprietary
0x000c_bb78
Instances = 1
Instances = 1
Offset = 0.11
Offset = 0.17
Mode = R/W
Mode = R/W
Parameters
10
Value
NA
NA
11
memory_device[5:0]
4
1
4
1
12
13
14
15
The device that experienced the parity error.
The address of the parity error.
16
17
18
19
20
memory_address[14:0]
21
22
Description
23
8
24
7
25
6
26
5
27
4
28
3
ET4148-50
29
2
30
1
31
0
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