L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 10

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Pin Descriptions
Table 4. Supervisor PCI Pins
10
PCI_RST_N
PCI_CLK
AD(31:0)
CBE[3:0]_N
PAR
FRAME_N
IRDY_N
TRDY_N
DEVSEL_N
STOP_N
PERR_N
SERR_N
IDSEL
REQ_N
GNT_N
INTA_N
LOCK_N
Pin Name
CMOS output AB31
CMOS output
CMOS input
CMOS input
CMOS input
CMOS input
CMOS input
(open drain)
(continued)
CMOS I/O
CMOS I/O
CMOS I/O
CMOS I/O
CMOS I/O
CMOS I/O
CMOS I/O
CMOS I/O
CMOS I/O
CMOS I/O
Type
AA27
AL28
31{AB30}, 30{AB28}, 29{AA26},
28{AC30}, 27{AC31}, 26{AB26},
25{AC27}, 24{AD31}, 23{AC29},
22{AD28}, 21{AD27}, 20{AC26},
19{AD26}, 18{AE27}, 17{AF31},
16{AE29}, 15{AH29}, 14{AJ30},
13{AJ31}, 12{AK31}, 11{AL30},
10{AK29}, 09{AL29}, 08{AK28},
07{AJ28}, 06{AG25}, 05{AK27},
04{AF25}, 03{AH27}, 02{AG26},
01{AJ27}, 00{AH26}
3{AD30}, 2{AE30}, 1{AH30},
0{AA29}
AG29
AE26
AF30
AF29
AF27
AG28
AG31
AG30
AD29
AB29
AA28
AF28
Agere Systems - Proprietary
Pin #s
PCI reset. Active-low.
PCI bus clock.
PCI address and data bus.
PCI command and byte-enable signals.
Active-low.
PCI parity signal.
PCI cycle frame signal. Active-low.
PCI initiator ready signal. Active-low.
PCI target ready signal. Active-low.
PCI device select signal. Active-low.
PCI stop signal. Active-low.
PCI parity error signal. Active-low.
PCI system error signal. Active-low.
PCI initialization device select signal.
PCI bus request signal. Active-low.
PCI bus grant signal. Active-low.
PCI interrupt. Active-low.
PCI lock signal. Active-low.
Preliminary Data Sheet
Description
Agere Systems Inc.
April 2006