L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 246

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Preliminary Data Sheet
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
April 2006
Appendix A: Registers
(continued)
Supervisor_Tx_Fifo_Limit
(continued)
This register is used to define the physical characteristics of the two supervisor transmit FIFOs. These FIFOs
reside within the supervisor’s memory space.
There are two instances of the three-field record diagrammed above. The record at offset zero corresponds to
transmit FIFO zero. Transmit FIFO zero is the low-priority FIFO. Transmit FIFO one is the high-priority FIFO. If
transmit FIFO one is nonempty, it is serviced until empty prior to continuing to service transmit FIFO zero.
tx_fifo_start_ptr[31:2] identifies the first physical location of a transmit FIFO. tx_fifo_end_ptr[31:2]
identifies the last physical location of a transmit FIFO. tx_fifo_start_ptr[31:2] must be less than
tx_fifo_end_ptr[31:2]. These values are established during initialization and must be left static during nor-
mal operation.
As the user adds entries to a transmit FIFO, it advances tx_fifo_last_ptr[31:2] to always point to the last
FIFO entry. The ET4148-50 interprets this value and uses it to determine when the FIFO is empty, nonempty, or
full.
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Agere Systems Inc.
Agere Systems - Proprietary