L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 173

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Packet_Buffer_Priority_Table
Description: Maps the 4-bit packet priority value to one of eight transmit queues.
Table 229. Packet_Buffer_Priority_Table Register Parameters
Table 230. Packet_Buffer_Priority_Table Field Parameters
The 16 levels of priority utilized during ingress packet processing are used to select one of eight transmit queues
associated with each transmit port. This table is used to map between various priority levels and queues. This table
is addressed by the packet’s priority level and returns the 3-bit queue selection value:
storage_priority[2:0].
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
storage_priority_{0..15}[2:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
Field Name
1
2
3
4
Figure 166. Packet_Buffer_Priority_Table Register Diagram
5
6
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
7
8
9
Agere Systems - Proprietary
Instances = 1
10
Offset = 0.29
Mode = R/W
Parameters
0x000c_bc00
11
Value
12
NA
64
16
1
1
4
13
14
15
16
Storage priority value.
17
18
19
20
21
22
Description
23
8
24
7
25
6
26
5
27
4
28
3
ET4148-50
29
2
30
1
31
0
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