L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 166

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Packet_Buffer_Ind
Description: Provides supervisor indications from packet_buffer.
Table 219. Packet_Buffer_Ind Register Parameters
Table 220. Packet_Buffer_Ind Field Parameters
166
packet_buffer_parity_error
free_buffer_list_parity_error
free_descriptor_list_parity_error
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
12
16
20
24
28
0
4
8
Parameter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Field Name
1
2
3
4
5
6
Figure 160. Packet_Buffer_Ind Register Diagram
7
(continued)
8
0x000c_bb40
Instances = 1
Instances = 1
Instances = 1
Offset = 0.25
Offset = 0.26
Offset = 0.27
9
Mode = R/W
Mode = R/W
Mode = R/W
Parameters
Value
NA
NA
32
10
1
4
1
Agere Systems - Proprietary
11
12
13
When a parity error occurs within the packet buffer memory,
this indication is asserted. The location of the error is deter-
mined by reading Packet_Buffer_Parity_Error_Info.
This indication is reset by writing a one to this bit location.
When a parity error occurs within the free buffer list memory,
this indication is asserted. The location of the error is deter-
mined by reading
Packet_Buffer_Parity_Error_Info. This indication is
reset by writing a one to this bit location.
When a parity error occurs within the free descriptor list
memory, this indication is asserted. The location of the error
is determined by reading
Packet_Buffer_Parity_Error_Info. This indication is
reset by writing a one to this bit location.
14
15
16
17
18
19
20
21
Description
22
23
8
24
7
Preliminary Data Sheet
25
6
26
5
27
4
Agere Systems Inc.
28
3
29
2
April 2006
30
1
31
0