L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 72

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix A: Registers
Acl_Deny_Packets
Description: The number of packets denied access by the ACL function.
Table 46. Acl_Deny_Packets Register Parameters
Table 47. Acl_Deny_Packets Field Parameters
72
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
acl_deny_packets[27:0]
0
Parameter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Field Name
2
3
4
5
6
7
(continued)
0x0004_2508
8
Value
Figure 38. Acl_Deny_Packets Diagram
9
NA
NA
4
1
4
1
10
Instances = 1
Mode = R/W
Parameters
Offset = 0.4
Agere Systems - Proprietary
11
12
13
14
acl_deny_packets[27:0]
15
16
This counter is incremented each time a packet is
denied by the ACL function. This counter does not
stick at its maximum value, nor is any indication of
a rollover provided to the supervisor. Therefore, the
supervisor must sample this register often enough
to prevent an undetected rollover.
17
18
19
20
21
22
23
8
Description
24
7
Preliminary Data Sheet
25
6
26
5
27
4
Agere Systems Inc.
28
3
29
2
April 2006
30
1
31
0