L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 270

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

ET4148-50
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
Appendix B: Configuration
Ethernet Interfaces
Logical Ports. Link aggregation enables the possibility of a single MAC source address to appear on several phys-
ical links nearly simultaneously. Ordinarily, the appearance of a MAC source address on a receive port that is differ-
ent than the one listed in the address table triggers an address learning event. However, for the ports within an
aggregate, all of the ports in that aggregate are valid receive ports for any particular source address. Hence, for
address learning purposes, the concept of a logical port is used.
Physical ports are mapped to logic ports through the use of the Layer_2_Logical_Port_Table register. This table
is addressed by the physical receive port number, and it returns a logical port number. For an aggregate of links, all
of the physical receive ports that are part of the link should return a common logical port number that is equal to the
lowest physical port number of the ports in the aggregate. For those ports that are not part of an aggregate, this
table should be configured to return those ports’ physical port number. Complying with the preceding recommenda-
tion is not essential. Alternate methods of configuring this table may be employed. The only important criterion is
that all ports in an aggregate must share a common, logical port number.
Link Selection. Packets received on any of the ports that make up a particular aggregate are treated identically by
the ET4148-50. Transmit packets may be transmitted by any of the ports of an aggregate, with the actual transmit
port being selected arbitrarily. The only requirement for transmit port selection is that all packets that may be part of
a particular conversation or flow use a common physical port.
The ET4148-50 uses an arithmetic reduction of the receive packet’s MAC destination and source address values
to arrive at a 3-bit link selection value; enabling a one-of-eight selection.
Destination Maps. In support of link aggregates, the Layer_2_Dest_Map_Table must be configured appropri-
ately. If an aggregate is the intended destination for a particular address table entry/destination map association,
then all of the bits corresponding to the ports in the aggregate must be asserted in the destination map. In other
words, the destination map must be set up as if the packet is to be multicast to all of the ports in the aggregate.
Aggregate masks are subsequently used to select a single port per aggregate.
Aggregate Masks. A total of eight aggregate masks are available via Layer_2_Aggregation_Mask_Table.
These eight masks serve all of the possible aggregates that may be configured in the system.
Every physical transmit port can be thought of as belonging to some form of an aggregate. Conceptually, even a
single-port aggregate is supported. The pattern of mask bits programmed into the
Layer_2_Aggregation_Mask_Table is determined by the number of ports in the aggregate. Membership levels
of 1 through 8 ports are allowed, though 1, 2, 4, and 8 are likely to be the most commonly used. The following table
shows the entries for aggregates of various port-counts.
Table 380. Aggregate Mask Patterns
270
Aggregate Mask Number
0
1
2
3
4
5
6
7
(continued)
(continued)
Agere Systems - Proprietary
1 Port
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
Mask Patterns for Various Ports Per Aggregate
2 Ports
01
10
01
10
01
10
01
10
2
2
2
2
2
2
2
2
4 Ports
0111
1011
1101
1110
0111
1011
1101
1110
Preliminary Data Sheet
2
2
2
2
2
2
2
2
Agere Systems Inc.
10111111
11011111
11101111
11110111
11111011
11111101
01111111
11111110
8 Ports
April 2006
2
2
2
2
2
2
2
2