L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 101

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Layer_2_Active_Port_Map
Defines which ports are enabled for the normal forwarding of traffic.
Table 103. Layer_2_Active_Port_Map Register Parameters
Table 104. Layer_2_Active_Port_Map Field Parameters
This field is used to identify those ports that are enabled to forward Ethernet traffic in a normal manner. This infor-
mation is used in determining whether or not a packet has been prevented from being forwarded due to VLAN mis-
matches.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
active_port_map[57:0]
REFERENCE
0
4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
PORT
1
Parameter
Field Name
2
SU7
57
3
SU6
56
4
5
6
Figure 74. Layer_2_Active_Port_Map Register Diagram
7
SU1
51
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
SU0
50
9
Instances = 1
Mode = R/W
Parameters
Offset = 0.6
Figure 75. Port Numbering Scheme
0x000c_4620
XG1
10
49
PORT NUMBERING SCHEME
Agere Systems - Proprietary
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
Value
11
XG0
NA
NA
48
8
1
8
1
12
G47
47
13
active_port_map[31:0]
G46
14
46
The active port map value. Each bit in the
map corresponds to an Ethernet port or one of
the supervisor’s queues.
15
G45
45
active_port_map[57:32]
16
G44
44
17
18
19
Description
20
21
G3
3
22
G2
2
23
8
G1
1
24
7
25
G0
6
0
26
5
27
4
28
ET4148-50
3
29
2
30
1
101
31
0