DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 945

IC H8S/2117 MCU FLASH 145TFLGA

DF2117VLP20V

Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet

Specifications of DF2117VLP20V

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
A.
Table A.1
[Legend]
H:
L:
T:
keep:
DDR:
Port Name
Pin Name
Port 1
Port 2
Port 3
Port 4
Ports 52 to 50
Port 6
Ports 7 and E4 to
E1
Port 8
Port 97
Port 96
φ,
EXCL
Ports 95 to 90
Ports A to D,
F, G, and H5 to H0
Port E0
Port I
Port J
High level
Low level
High impedance
Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up
MOS remains on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR.
Data direction register
I/O Port States in Each Pin State
I/O Port States in Each Pin State
T
T
T
Reset
T
T
T
T
T
T
T
T
T
T
T
T
Software
Standby Mode
keep
keep
keep
keep
keep
keep
T
keep
keep
[DDR = 1]H
[DDR = 0]T
keep
keep
T
keep
keep
Appendix
Watch Mode
keep
keep
keep
keep
keep
keep
T
keep
keep
EXCL input/
keep
keep
keep
ExEXCL input/T
keep
keep
Rev. 3.00 Sep. 28, 2009 Page 899 of 910
Sleep Mode
keep
keep
keep
keep
keep
keep
T
keep
keep
[DDR = 1]
Clock output
[DDR = 0]T
keep
keep
T
keep
keep
REJ09B0350-0300
Program
Execution State
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Input port
I/O port
I/O port
Clock output/
EXCL input/
Input port
I/O port
I/O port
ExEXCL input/
input port
I/O port
I/O port
Appendix

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